According to a report by IEEE Spectrum, OpenAI has embedded its own large language models directly into the design workflow of an internal chip codenamed Jalapeño. The company, best known for its consumer-facing language models, has spent recent months developing custom silicon intended for its inference and training infrastructure, as part of a broader partnership with foundries and component makers such as Broadcom.
The report describes a concrete application of generative AI to electronics engineering: engineers reportedly used LLMs to generate and verify hardware description code, automate repetitive documentation tasks, and speed up review cycles for technical specifications. This kind of use fits a wider industry trend, as companies like Synopsys and Cadence already integrate AI assistants into their electronic design automation (EDA) tools.
The case illustrates a form of circularity typical of major AI companies: using their own products to build the hardware infrastructure that will eventually run them. For OpenAI, mastering chip design is a strategic move to reduce reliance on Nvidia, while also aiming to cut costs and shorten development timelines for specialized inference hardware at scale.
The article does not claim that LLMs designed the chip end-to-end, but rather that they served as assistive tools for specific tasks within the design pipeline. Based on what has been published, it remains hard to gauge the actual productivity gains achieved, but the initiative confirms that leading AI labs are actively exploring the automation of their own hardware engineering processes.